Rockchip RK3572 is a high-performance processor targeting edge computing, AIoT devices, smart terminals, and multimedia applications. The chip adopts a big.LITTLE CPU architecture and integrates a GPU, NPU, video codec, a 12MP ISP, and a rich set of high-speed and industrial communication interfaces — balancing general-purpose computing, edge AI, image capture, video processing, and device connectivity.
This article compiles the key technical parameters of the RK3572 based on the *Rockchip RK3572 Datasheet V1.1*.

Parameter | RK3572 Specification |
CPU Architecture | 2×Cortex-A73 + 2×Cortex-A53 + 4×Cortex-A53 |
Instruction Set | Armv8-A, with NEON and Armv8 cryptography extensions |
CPU Frequency | 2.2GHz + 2.1GHz + 2.1GHz |
GPU | Arm Mali-G310V2 MC1 |
Graphics APIs | OpenGL ES 1.1/2.0/3.2, OpenCL 3.0 Full Profile, Vulkan 1.4 |
2D Engine | Rockchip RGA 2.5 |
NPU Compute | Up to 4 TOPS (INT8) |
AI Data Types | INT4, INT8, INT16, FP4, FP8, FP16, BF16 |
Memory Type | LPDDR4, LPDDR4X, LPDDR5, LPDDR5X |
Memory Rate | LPDDR4/4X-4266, LPDDR5/5X-5500 |
Max Addressable Space | 16GB |
Video Decoding | H.265, VP9, AV1, AVS2 up to 8K@30fps or 4K@120fps; H.264 up to 4K@60fps |
Video Encoding | H.264/H.265 up to 4K@40fps |
JPEG/MJPEG | Up to 4K@60fps |
ISP | Single-channel 12MP ISP 3.5, max input 4096×3072 |
Camera Interface | 2× 4-lane MIPI CSI-2, splittable into 4× 2-lane; DVP supported |
Display Capability | Video Port 0 up to 4K@60Hz; Video Port 1 up to 2048×1080@60Hz |
Display Interface | HDMI 2.1/eDP 1.3 Combo, MIPI DSI 1.2, RGB/BT.656/BT.1120, EBC |
Networking | 2× 10/100/1000Mbps Ethernet MAC |
High-speed Expansion | PCIe 2.1, SATA 3.1, USB 3.0 Combo PHY |
Storage Interface | eMMC 5.1, UFS 2.0, SD 3.0, FSPI |
General-purpose I/O | 12×UART, 5×SPI, 10×I²C, 1×I3C, 4×CAN |
Analog Acquisition | 8-channel 12-bit SARADC, up to 1MS/s |
Package | FCCSP550L, 14.3mm×15.5mm |
Recommended Ambient Temperature | 0℃ to 80℃ |
The RK3572 integrates two Cortex-A73 cores and six Cortex-A53 cores, forming an octa-core heterogeneous CPU architecture.
Among them, the Cortex-A73 focuses on general-purpose computing performance under higher loads, suited for data processing, complex applications, and multitasking; the Cortex-A53 emphasizes energy efficiency, handling system services, device communication, and background tasks.
CPU Cluster | Core Count | L1 I-Cache per Core | L1 D-Cache per Core | Shared L2 Cache |
Cortex-A73 Cluster | 2 cores | 64KB | 32KB | 512KB |
Cortex-A53 Cluster 0 | 4 cores | 32KB | 32KB | 512KB |
Cortex-A53 Cluster 1 | 2 cores | 32KB | 32KB | 256KB |
The CPU supports the complete Armv8-A instruction set, NEON SIMD, and Armv8 cryptography extensions, which can accelerate multimedia processing, signal processing, data computation, and certain cryptographic tasks.
For power management, the A73 and A53 clusters adopt two independent voltage domains, supporting DVFS (Dynamic Voltage and Frequency Scaling). Each CPU core complex also features an independent power domain that can be switched on/off based on application load.
The RK3572 integrates a Rockchip NPU with a nominal INT8 compute of up to 4 TOPS.
Supported NPU data precisions include:
l INT4, INT8, and INT16;
l FP4, FP8, and FP16;
l BF16;
l W4A16 asymmetric MAC operations.
Supported deep-learning frameworks include TensorFlow, Caffe, TFLite, PyTorch, ONNX NN, Android NN, and MXNet, among others.
The RK3572 NPU can be used for image classification, object detection, OCR recognition, equipment-status recognition, lightweight anomaly analysis, and other edge inference tasks.
The RK3572 integrates an Arm Mali-G310V2 MC1 GPU, supporting:
l OpenGL ES 1.1, 2.0, and 3.2;
l OpenCL 3.0 Full Profile;
l Vulkan 1.4;
l AFBC framebuffer compression.
The GPU can handle 3D interface rendering, graphics acceleration, visual interaction, and some general-purpose computing tasks.
The chip also integrates a Rockchip RGA 2.5 2D graphics engine, supporting image scaling, rotation, mirroring, alpha blending, color fill, and format conversion.
The RGA supports source images up to 8192×8192 pixels, with target images up to 4096×4096 pixels; the scaling ratio ranges from 1/16 to 16×, and supports 0°, 90°, 180°, and 270° rotation.
In addition to RGA, the RK3572 provides a VDPP (Video and Display Post-Processing) module capable of deinterlacing, scaling, sharpening, dynamic contrast adjustment, edge smoothing, and image-pyramid downsampling.
The RK3572 integrates hardware video decoders and encoders, suitable for local video playback, video capture, recording storage, image analysis, and multimedia terminal applications.
Codec | Profile/Level | Max Specification |
H.264/AVC | Main10 Level 5.2 | 4K@60fps |
H.265/HEVC | Main10 Level 6.0 | 8K@30fps or 4K@120fps |
VP9 | Profile 0/2 Level 6.0 | 8K@30fps or 4K@120fps |
AVS2 | Profile 0/2 Level 8.2.120 | 8K@30fps or 4K@120fps |
AV1 | Main10 Level 6.0 | 8K@30fps or 4K@120fps |
H.264 MVC | — | 4K@60fps |
Codec | Profile/Level | Max Specification |
H.264/AVC | High Level 5.0 | 4K@40fps |
H.265/HEVC | Main Level 5.0 | 4K@40fps |
MJPEG Encoding | Baseline | 4K@60fps |
MJPEG Decoding | — | 4K@60fps |
The H.264 and H.265 encoders support multi-stream encoding, which can be used for main-stream and sub-stream output, video storage, and remote transmission scenarios.
The RK3572 integrates a single-channel ISP 3.5, supporting image processing up to 12MP, with a maximum input resolution of 4096×3072 and a minimum input resolution of 264×264.
Key image-processing functions supported by the ISP include:
l 3A statistics such as AE, AF, and AWB;
l Fixed-pattern noise (FPN) removal and dead-pixel correction;
l PDAF (Phase Detection Auto Focus);
l Lens shading correction;
l Bayer-domain 3D noise reduction;
l Chromatic aberration correction;
l Dual-frame HDR synthesis and dynamic range compression;
l Demosaic and color correction;
l Defogging and image enhancement;
l Horizontal and vertical lens distortion correction;
l Luma and chroma noise reduction;
l Image sharpening and color space conversion.
For camera input, the chip provides two MIPI CSI-2 interfaces, each supporting 4-lane D-PHY 1.2, and can also be configured as two 2-lane interfaces, thus forming up to four 2-lane ports. Each port supports 4 virtual channels.
In addition, the RK3572 provides a DVP interface supporting 8/10/12/16-bit data widths and BT.601, BT.656, and BT.1120 inputs.
The RK3572 provides two internal display Video Ports:
Display Channel | Max Resolution | Bit Depth |
Video Port 0 | 4096×2160@60Hz | 10-bit |
Video Port 1 | 2048×1080@60Hz | 8-bit |
Display output resources include:
l HDMI 2.1;
l eDP 1.3, compatible with DisplayPort 1.2;
l MIPI DSI 1.2;
l RGB, BT.656, and BT.1120 parallel interfaces;
l EBC (E-paper Display Controller) interface.
HDMI and eDP share a Combo PHY. HDMI supports up to 4K@60Hz, with RGB, YUV444, YUV422, YUV420, and 8/10-bit output; eDP provides 4 physical lanes, each up to 5.4Gbps, also supporting up to 4K@60Hz.
MIPI DSI provides 4 data lanes, each up to 2.5Gbps. The parallel display interface supports up to 1920×1080@60Hz.
The EBC interface targets e-paper displays, supporting up to 1872×1404 resolution, a 16-bit data bus, and up to 32 grayscale levels.
The RK3572 supports LPDDR4, LPDDR4X, LPDDR5, and LPDDR5X memory.
Memory Type | Max Data Rate |
LPDDR4/LPDDR4X | 4266Mbps |
LPDDR5/LPDDR5X | 5500Mbps |
The memory interface is a single-channel 32-bit data width, supporting up to 4 ranks per channel, with a total addressable space of up to 16GB.
The datasheet specifically notes: when the rank count is 2, LPDDR4/LPDDR4X R17 is not supported.
Storage interfaces supported by the RK3572 include eMMC 5.1, UFS 2.0, SD 3.0, and FSPI.
The BootROM supports booting from FSPI, eMMC, UFS, and SD cards, and also supports downloading system code via the USB DRD interface.
The chip also integrates 16KB of PMU SRAM and 512KB of system SRAM.
The RK3572 integrates two Gigabit Ethernet MACs supporting 10/100/1000Mbps, configurable with RGMII or RMII interfaces.
The high-speed expansion part consists of three single-lane Combo interface groups:
l Two PCIe 2.1/SATA 3.1/USB 3.0 Combo interfaces;
l One PCIe 2.1/SATA 3.1 Combo interface.
Interface | Key Capability |
PCIe | PCIe 2.1, up to 5GT/s, Root Complex mode only |
SATA | SATA 3.1, AHCI 1.3.1, up to 6GT/s, eSATA supported |
USB 3.0 | Up to 5Gbps, Host and Device dual-role |
SDIO | SDIO 3.0, 4-bit data bus |
Since these interfaces use a Combo PHY, the same PHY group cannot operate in PCIe, SATA, and USB modes simultaneously. Hardware design must allocate functions according to application requirements.
The RK3572 provides a rich set of low-speed communication and industrial control resources.
Interface Type | On-chip Resources |
UART | 12 channels, up to 8Mbps |
RS-485 Support | UART1–UART11 support RS-485 |
SPI | 5 channels, each with 2 chip selects |
I²C | 10 master controllers, standard mode and 400kbps fast mode |
I3C | 1 master controller, SDR, IBI, and Hot-Join supported |
CAN | 4 channels, compliant with ISO 11898-1:2003 |
PWM | 16 channels |
SARADC | 8 single-ended inputs, 12-bit, up to 1MS/s |
GPIO | Multiple GPIO groups, level and edge interrupt supported |
DSMC | 8-bit or 16-bit serial transfer with up to 4 chip selects |
The RK3572 provides 6 SAI (Serial Audio Interface) ports supporting I²S, TDM, and PCM modes, with sampling rates up to 192kHz and sample precision of 16–32 bits.
The chip also integrates:
l 3 SPDIF transmit resources;
l 2 SPDIF receive resources;
l Up to 8-channel PDM input;
l 4-channel ASRC (Asynchronous Sample Rate Converter);
l 2-channel digital DAC.
These resources can be used for voice capture, multi-channel audio, digital audio output, and multimedia applications with display devices.
The RK3572 supports Arm TrustZone and integrates an independent cryptographic engine.
The cryptographic engine supports:
l AES, DES, 3DES, and SM4;
l SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, MD5, and SM3;
l RSA, ECC, and SM2;
l HMAC;
l Key Ladder;
l Secure OTP.
Among these, RSA supports 512–4096-bit keys and ECC supports 192, 224, and 256 bits.
The chip also supports DDR data scrambling, secure debug, secure DFT testing, a secure operating system, and secure/non-secure access control. The system SRAM can be divided into 4 access regions, and the external DDR into 16 access regions, to control access permissions for different bus masters.
Reliability resources include 5 non-secure watchdogs, 1 secure watchdog, multiple 64-bit timers, and 4 peripheral DMA controllers.
The RK3572 integrates a PMU (Power Management Unit) providing 7 independent voltage domains and 23 independent power domains. Software can control the power and clock of different modules according to application scenarios, reducing power consumption under standby or light-load conditions.
The chip also integrates a Nuclei N320 RISC-V MCU, equipped with:
l 24KB ILM;
l 8KB instruction cache;
l 8KB data cache;
l JTAG debug interface.
The CPU and MCU communicate via a 14-channel Mailbox. This heterogeneous structure can be used for auxiliary control, system management, or tasks requiring independent real-time processing.
The RK3572 adopts the FCCSP550L package.
Item | Parameter |
Package Type | FCCSP550L |
Package Size | 14.3mm×15.5mm |
Solder Ball Size | 0.25mm |
Solder Ball Pitch | Mixed 0.42mm, 0.52mm, and 0.65mm |
Recommended Ambient Operating Temperature | 0℃ to 80℃ |
Storage Temperature | -40℃ to 125℃ |
Max Junction Temperature | 125℃ |
The on-chip TSADC supports a temperature detection range of -40℃ to 125℃ with 1℃ resolution. This range represents the detection capability of the on-chip temperature sensor and cannot be directly equated with the operating temperature of the product or the entire system.
Based on the CPU, NPU, video, display, and interface resources, the RK3572 is suitable for the following types of applications:
l Edge AI computing devices;
l Machine vision and image capture terminals;
l AIoT smart terminals;
l Industrial control and data processing equipment;
l Multimedia information terminals;
l Smart displays and industrial HMI (Human-Machine Interface);
l Multi-channel video decoding and recording devices;
l Device management and edge data processing platforms;
l E-paper display terminals;
l Embedded devices requiring dual Gigabit Ethernet and high-speed storage expansion.
The Rockchip RK3572 adopts 2 Cortex-A73 cores and 6 Cortex-A53 cores, integrating a Mali-G310 GPU, 4 TOPS NPU, 12MP ISP, and an 8K video decoding module.
In terms of interfaces, the chip supports LPDDR4/4X and LPDDR5/5X memory, eMMC 5.1, UFS 2.0, PCIe 2.1, SATA 3.1, USB 3.0, dual Gigabit Ethernet, MIPI CSI, HDMI, eDP, MIPI DSI, as well as UART, SPI, I²C, I3C, and CAN communication resources.
Its characteristic is not simply pursuing peak performance of a single module, but integrating general-purpose computing, edge AI, image capture, video processing, display output, and device connectivity on a single platform — making it suitable for edge computing and AIoT products with comprehensive requirements for performance, interfaces, and power consumption.
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